1. Field of the Invention
The present invention relates to a method of fabricating an organic light emitting diode (OLED) display, and more particularly, to a method of fabricating an OLED that has an enhanced aperture ratio by forming a first electrode to make it overlap with a scan line, a common power supply line Vdd and/or a data line Vdata and etching a pixel defining layer (PDL) by backside exposure.
2. Description of the Related Art
An OLED display is a flat panel display that is a self-emissive display, and has a wide viewing angle, a fast response speed, a thin thickness, a low fabrication cost, a high contrast ratio, and similar characteristics. In an OLED, holes and electrons are recombined in an emission layer to generate excitons so that light is emitted by energy generated from the excitons that are transitioned from an excited state to a ground state.
In general, OLED displays are classified into a passive matrix type and an active matrix type according to the manner of driving N×M pixels arranged in a matrix form. Passive matrix OLED displays have anode electrodes and a cathode electrodes perpendicular to each other and select a line to be driven, whereas the active matrix OLED displays allow a voltage to be maintained through the capacitance of a capacitor by connecting a thin film transistor and the capacitor to each pixel electrode in each pixel of a display region.
Each unit pixel basically has a switching transistor, a driving transistor, a capacitor, and an electroluminescent (EL) element in the active matrix OLED display. A common power supply voltage Vdd is supplied to the driving transistor and the capacitor from the power supply line, and the power supply line acts to control a current flowing toward the EL element through the driving transistor.
FIG. 1 is a plan view of a conventional active matrix OLED 140.
Referring to FIG. 1, the active matrix OLED 140 includes a scan line 10 for outputting a selection signal, and a data line 20 for outputting a data signal. In addition, it includes a common power supply line 30 arranged on the right and left sides of a pixel region to supply a power supply voltage, a switching transistor 40, a driving transistor 50, a capacitor 60, and an EL element (120). The driving transistor 50 includes a semiconductor layer 70, a gate electrode 80, and source and drain electrodes 90a and 90b, and contact holes 85 for connecting the source and drain electrodes 90a and 90b to the semiconductor layer 70, a via hole 95 for connecting one of the source and drain electrodes 90a and 90b to a first electrode 100, and a pixel defining layer 110 are disposed on the semiconductor layer 70. The pixel defining layer 110 defines an organic layer 120 and a pixel region and is formed on the entire surface of the substrate except a region where the organic layer 120 including at least an organic emission layer is formed.
In addition, a region where the organic layer 120 is formed on a portion of the first electrode 100 exposed by etching becomes an opening portion e, and in this case, an aperture ratio is defined as d1×d2.
The opening portion e of the conventional OLED has a first dimension d1 which is 41 μm and a second dimension d2 which is 134 μm, so that the aperture ratio becomes 5,494 μm2 which is equal to 41 μm×134 μm.
Dead space d3 cannot be used as the opening portion on the pixel region, and is present on each of the right, left, and lower sides and has a width of 3 μm. Accordingly, dead space, which cannot be used as part of the opening portion, with a size of at least 9 μm is present in the unit pixel of the OLED.
FIG. 2 is a cross-sectional view taken along a line A-A′ of FIG. 1 in the conventional active matrix OLED.
Referring to FIG. 2, the conventional active matrix OLED includes a substrate 62 having an opening region a, a transistor region b, and a metal line region c, and a buffer layer 66 is formed on the entire surface of the substrate 62. A semiconductor layer 70 including source and drain regions 70a and 70c and a channel region 70b is patterned on a predetermined region of the buffer layer 66 in the transistor region b. A gate insulating layer 67 is then formed on the entire surface of the semiconductor layer 70.
Subsequently, a gate electrode 80 corresponding to the channel region 70b of the semiconductor layer 70 is formed on the gate insulating layer 67 of the transistor region b. An interlayer-insulating layer 83 is formed on the entire surface of the gate electrode 80. The source and drain regions 70a and 70c of the semiconductor layer 70 are then connected to source and drain electrodes 90a and 90b via a contact hole 85 formed within the interlayer-insulating layer 83 of the transistor region b. Accordingly, a thin film transistor comprising the semiconductor layer 70, the gate electrode 80, and the source and drain electrodes 90a and 90b is formed. In this case, a data line 20 and a common power supply line 30 formed of the same material as the source and drain electrodes 90a and 90b are also formed on the interlayer-insulating layer 83 of the metal line region c at the time of forming the source and drain electrodes 90a and 90b of the transistor region b.
Subsequently, a passivation layer 91 is formed on the source and drain electrodes 90a and 90b, the data line 20, and the common power supply line 30. A via hole 95 exposing one of the source and drain electrodes 90a and 90b is formed on the passivation layer 91 of the transistor region b, and a first electrode 100 which is in contact with one of the source and drain electrodes 90a and 90b via the via hole 95 and extends onto the passivation layer 91 of the opening region a is formed. In this case, source and drain electrode materials forming the data line 20 and the common power supply line 30 do not overlap the first electrode 100.
Subsequently, a pixel defining layer (PDL) 110 having the opening portion e is formed on the first electrode 100 of the opening region a and the passivation layer 91 of the transistor region b and the metal line region c. Referring back to FIG. 1, the pixel defining layer 110 defines a pixel region and is formed on the entire surface of the substrate except the region where the organic layer 120 is formed.
Subsequently, an organic layer 120 including at least an organic emission layer is formed on the first electrode 100 exposed within the opening portion e, and a second electrode (not shown) is formed on the entire surface of the substrate including the organic layer 120.
However, the opening portion e for exposing the first electrode is formed by wet-etching the pixel defining layer which causes a limitation on opening an area on the first electrode due to isotropic etching, so that a dead space occurs on the pixel region, which in turn causes the opening to be narrow such that the aperture ratio decreases.